This invention relates to field-effect transistors (FET's) and to methods of making such transistors. More particularly, this invention is concerned with a method for making self-aligned gate (SAG) transistors for use in both analog and digital integrated circuits and the resultant structure.
Previous SAG FET's have employed a symmetrical structure, with highly doped n+ regions on either side of the self-aligned gate electrode. Although this structure is relatively simple to fabricate, it has several disadvantages. First, the close proximity of the n+ region to the drain side of the gate causes a large reduction in the gate-drain breakdown voltage, which severely limits the ultimate power-handling capability of the FET. Furthermore, the high doping of the n+ region also increases the gate-drain capacitance. Finally, the close spacing between source and drain n+ regions increases the parasitic substrate current, thereby decreasing the output resistance of the FET. All of these have adverse effects on the performance of a self-aligned FET when used in either analog or digital circuits, but the use of a self-aligned FET to handle high-frequency analog signals is particularly impaired by the above disadvantages of a symmetrical device structure.
Certain copending applications describe pertinent processing techniques also employed in this invention and are generally related to similar devices. For example see a patent application entitled "A Method of Making Self-Aligned GaAs Digital Integrated Circuits" filed on Oct. 21, 1985 as Ser. No. T.Q. 789,523 now abandoned for R. A. Sadler et al. See also a copending application entitled "Methods of Making Self-Aligned GaAs Devices" filed on Jan. 12, 1987, Ser. No. 002,083 now U.S. Pat. No. 4,782,032 for A. E. Geissberger et al. See also a copending patent application entitled "A Method of Making Self-Aligned Field-Effect Transistors" filed on Jan. 12, 1987, Ser. No. 002,084 now abandoned for A. E. Geissberger et al. These applications generally relate to field-effect devices as for example other types of devices relating to those described in this application and utilize similar processing techniques to accomplish certain results, and all of the above applications are assigned to the assignee herein.